This invention relates to digital delay-locked loop (DLL) circuits. More particularly, this invention relates to digital delay-locked loop circuits with hierarchical delay adjustment.
Digital delay-locked loop circuits typically generate a clock signal based on a periodic reference signal (e.g., from an oscillator) that maintains a specific phase relationship with that reference signal. Digital delay-locked loop circuits are often used, for example, in high-speed clocked memories such as synchronous dynamic random access memories (SDRAMs).
A digital delay-locked loop circuit generally includes a variable delay line, a phase mixer, a phase detector, and control logic. The variable delay line includes delay units that are used to delay the reference signal by a predetermined time period (i.e., phase). The number of delay units indicate the number of possible unit delays (i.e., tUDs) that can be generated by the variable delay line. For example, a variable delay line having five delay units can delay the reference signal by one of five unit delays (e.g., tUD, 2tUD, 3tUD, 4tUD, or 5tUD). Each unit delay is typically a predetermined time increment (e.g., 100 or 200 picoseconds (ps)), which can also be measured by predetermined phase increments (e.g., 10°, 15°, or 22.5°). The variable delay line is set by the control logic such that the variable delay line receives as input a reference signal and outputs two delayed reference signals having a one unit delay difference (tUD). The two delayed reference signals are input to the phase mixer. The phase mixer is also set by the control logic such that the phase mixer generates a clock signal having a phase between the phases of the two delayed reference signals. The phase detector compares the phase of the clock signal with the phase of the reference signal to determine whether the phase of the clock signal needs to be increased or decreased to better match the desired output phase of the clock signal. The phase detector sends a signal to the control logic indicating whether the phase of the clock signal needs to be increased or decreased. Based on the output of the phase detector, the control logic sends control signals to the variable delay line and the phase mixer.
In current digital delay-locked loop circuits, two stages of delay adjustment are provided. In a first stage, the variable delay line delays the reference signal by a predetermined time period or phase. In a second stage, the phase mixer provides an additional delay that is smaller than a unit delay from the variable delay line. The minimum delay adjustment for the variable delay line and phase mixer is limited by the amount of circuitry dedicated to providing the minimum delay adjustment and by the increase in characteristic load on the variable delay line and phase mixer that results when providing additional phases with smaller delays. Consequently, known digital delay-locked loop circuits typically generate a clock signal having one of only a limited, predetermined number of phases based on the reference signal.
In view of the foregoing, it would be desirable to provide a digital delay-locked loop circuit with hierarchical delay adjustment.